1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to apparatus and method for manufacturing complementary bipolar transistor structures.
2. Description of the Related Art
Conventional bipolar integrated circuit processes are typically based around the production of an NPN bipolar transistor structure such as that depicted in FIG. 1. In FIG. 1, a P-type substrate 10 has a N-type buried layer 12 in its upper surface. An N- epitaxial layer 14 is grown over substrate 10 and buried layer 12. P+ well regions 16 and 18 set in the upper surface of epitaxial layer 14 are used to create spaced-apart P- vertical isolation regions by downward diffusion when the device is heated. An N+ emitter region 24, a P+ base 26, and an N+ collector region 28 are created in the upper surface of epitaxial layer 14 using conventional techniques. Metal contacts 30, 32 and 34 are created for emitter 24, base 26, and collector 28 respectively. A negative voltage is applied to metal contact 36 to create a negative potential in vertical isolation regions 22 and 20, and substrate 10. An oxide layer 38 is then formed over the entire device, and thereafter a protective insulating layer 40 is formed.
Although the conventional fabrication technique used to manufacture the NPN transistor depicted in FIG. 1 has also been used to manufacture a lateral PNP bipolar transistor on the same wafer, the performance of the PNP transistor so made is poor compared to that of the NPN transistor.
Several processes have been developed to produce a high quality PNP bipolar transistor and NPN bipolar transistor on the same wafer wherein the PNP transistor is created using a sequence of process steps similar to that used in fabricating the NPN transistor. One prior art approach is depicted in FIG. 2. In FIG. 2, the NPN transistor's components have been given the same numerical labels as corresponding components in FIG. 1 since they have similar functions.
Regarding the PNP transistor shown on the left-hand side of FIG. 2, an N well region 42 is created to isolate the P+ tub isolation region 44 from substrate 10. N- epitaxial layer 14 is then grown over substrate 10, well 42, and P+ isolation region 44.
Next, P+ well regions 46 and 48 are set in the upper surface of epitaxial layer 14. When the device is heated, dopant ions from well regions 46 and 48 downwardly diffuse and meet with upwardly diffused ions from P+ tub isolation region 44 to create P- down isolation region 50. P+ well region 48 also serves as the collector for the PNP transistor.
The P+ emitter 52 and N+ base 54 are set in the upper surface of epitaxial layer 14 using a conventional technique such as ion implantation. Emitter contact 56, base contact 58, and collector contact 60 are deposited through windows in oxide layer 38 so that they contact emitter 52, base 54, and collector 48 respectively. The protective insulation layer 40 is then formed over the entire device.
Although the complementary bipolar transistor structure depicted in FIG. 2 achieves acceptable results, it requires four extra mask steps than are required over a standard bipolar process such as that depicted in FIG. 1.
The desirability of producing low-power digital circuitry to be used in conjunction with high performance analog circuitry has led to the incorporation of Bipolar transistors and Complementary Metal Oxide Semiconductor (CMOS) devices on the same wafer. In general, these "BiCMOS" fabrication techniques enable only one type of bipolar transistor to be fabricated on the same wafer as the CMOS device due to the complexity of adding both NPN and PNP bipolar transistors to an already complicated CMOS process, and due to the relatively large number of extra mask steps required to fabricate such a fully complementary BiCMOS device.